The present invention relates generally to semiconductor fabrication and more specifically to a method of integrating copper inductor, MIM capacitor and precision resistors in a copper IC.
Inductors with aluminum (Al) or copper (Cu) have been employed in integrated circuit (IC) technology, often with a stack of multiple metal films connected by vias to reduce the metal resistance. The metal-insulator-metal (MIM) is typically built with an intermediate metal (Al, titanium nitride (TiN), etc.) between interconnect metal layers and vias (tungsten (W)-plug or hot-Al flow) to contact the top MIM electrode. In the case of precision resistors, the high resistance metal is usually deposited specifically for its sole use as a resistor.
U.S. Pat. No. 5,926,359 to Greco et al. describes an interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode or the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer.
U.S. Pat. No. 5,652,173 to Kim et al. describes a monolithic microwave integrated circuit (MMIC) is produced by a method which forms multilevel conductive members, including thick low-loss metallic members.
U.S. Pat. No. 6,083,785 to Segawa et al. describes a method of manufacturing a semiconductor device having resistor film. An isolation is formed in a part of a P-well of a semiconductor substrate. A resistor film is formed on the isolation as a first conductor member. An insulating film covering the resistor film, except for contact formation regions, and an upper electrode film, as a second conductor member, are simultaneously formed with the formation of a gate electrode and a gate oxide film.
U.S. Pat. No. 5,268,315 to Prasad et al. describes an HBT IC process that can fabricate npn heterojunction bipolar transistors, Schottky diodes, MIM capacitors, spiral inductors and NiCr resistors.
U.S. Pat. No. 6,040,226 to Wojnarowski et al. describes a method for the manufacture of precision electronic components such as resistors, inductors and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials.
U.S. Pat. No. 5,370,766 to Desaigoudar et al. describes methods for fabrication of thin film inductors, inductor networks and integration with other passive and active devices.
U.S. Pat. No. 5,946,567 to Weng et al. describes a method for making metal capacitors for deep submicrometer processes for integrated circuits.
U.S. Pat. No. 6,117,747 to Shao et al. describes a method for fabricating a metal-oxide-metal capacitor using a dual damascene process.
U.S. Pat. No. 5,446,311 to Ewen et al. describes a monolithic high-Q inductor structure formed with multiple metallization levels in a conventional integrated circuit technology in which inductor turns utilize multiple levels to reduce the inductor resistance.
The article entitled xe2x80x9cIntegration of Thin Film MIM Capacitors and Resistors into Copper Metallization based RF-CMOS and Bi-CMOS Technologies;xe2x80x9d Peter Zurcher et al.; IEDM; pp. 00-153 to 00-156 (7.3.1 to 7.3.4); copyright 2000; describes high precision metal-insulator-metal (MIM) capacitors with a capacitance density of 1.6 fF/xcexcm2 and metal thin film resistors of 50 ohm/sq. sheet resistance and a negative temperature coefficient of resistivity smaller than 100 ppm/xc2x0 C. that have been integrated in a dual-inlaid Cu-based backend for mixed-signal applications.
The article entitled xe2x80x9cxe2x80x98System on a Chipxe2x80x99Technology Platform for 0.18 xcexcm Digital, Mixed Signal and eDRAM Application;xe2x80x9d R. Mahnkopf et al.; four (4) pages; presented at 1999 IEDM; copyright 1999; describes a 0.18 xcexcm high performance/low power technology platform which allows xe2x80x98systems on a chip integrationxe2x80x99 for a broad spectrum of products.
The article entitled xe2x80x9cSpiral Inductors and Transmission Lines in Silicon Technology Using Copper-Damascene Interconnects and Low-Loss Substrates;xe2x80x9d Joachim N. Burghartz et al.; pp. 1961 to 1968; copyright 1997; describes fabrication of spiral inductors and different types of transmission lines using copper damascene interconnects and high-resistivity silicon (HRS) or sapphire substrates.
The article entitled xe2x80x9cInterconnect Passive Components for Mixed Signal/RF Applications;xe2x80x9d Ariun Kar-Roy et al.; pp. 80 to 89; IEEE Trans on Microwave Theory and Techniques; Vol. 45 No. 10; October, 1997; describes performance issues of interconnect passive components and their integration into subtractive Al processes and dual damascene copper processes. Migration of capacitors towards high-k dielectrics such as Ta2O5, characterization of free lateral MIM capacitors and results of integration of photo-BCB as a thick dielectric to improve upon inductor Q are also presented.
The article entitled xe2x80x9cSingle Mask Metal-Insulator-Metal (MIM) Capacitor with Copper Damascene Metallization for Sub-0.18 xcexcm Mixed Mode Signal and System-on-a-Chip (SoC) Applications;xe2x80x9d Ruichen Liu et al.; presented at year 2000 IITC held Jun. 4 to 7, 2000; describes fabrication of low leakage, high linearity MIM capacitors directly on Cu by using a PECVD SiN as both the capacitor dielectric and the diffusion barrier for Cu.
Accordingly, it is an object of the present invention to provide a cost effective method of integrating copper inductor, MIM capacitor and precision resistors in a copper IC fabrication process.
Another object of the present invention is to provide a method of integrating copper inductor, MIM capacitor and precision resistors in a copper IC fabrication process using conventional equipment and materials.
A further object of the present invention is to provide a method of integrating copper inductor, MIM capacitor and precision resistors in a copper IC fabrication process with minimal extra masking or processing.
Yet another object of the present invention is to produce high performance components (high inductor Q (quality)-factor; high capacitance capacitors; and low temperature coefficient (Tcr) resistors).
Another object of the present invention is to fabricate high performance integrated circuit (IC) passive components (inductor, MIM capacitor, and precision resistor) compatible with copper interconnects and using conventional equipment and materials using a minimum of two masking steps.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, in the first embodiment, wafer is provided having an exposed top-most planar copper interconnect. The wafer being divided into one or more areas selected from the group consisting of: a spiral inductor area having an exposed planar copper interconnect bottom half of a stacked spiral inductor; a MIM capacitor area having an exposed planar copper interconnect bottom plate and an exposed planar copper interconnect contact point of a MIM capacitor; and a precision resistor area having a two exposed planar copper interconnect routing points of a precision resistor. A first insulator layer is formed over the structure. A metal layer is formed over the first insulator layer. A first patterned masking layer is formed over the metal layer covering at least a portion of the MIM capacitor area exposed planar copper interconnect bottom plate and at least a portion of the area between the precision resistor area planar copper interconnect routing points. The metal layer over the first dielectric insulator layer is etched, without substantially etching the underlying first dielectric insulator layer, using the patterned first masking layer as a mask, to form a metal top plate over at least a portion of the interconnect bottom plate of a MIM capacitor and a patterned metal layer portion between the two planar copper interconnect routing points of a precision resistor. A second insulator layer is formed over the structure. A second patterned masking layer is formed over the second insulator layer exposing portions of the second insulator layer over: the planar copper interconnect bottom half of a stacked spiral inductor; at least a portion of the metal top plate and at least a portion of the planar copper interconnect contact point of a MIM capacitor; and the two exposed planar copper interconnect routing points of a precision resistor. The second insulator layer is etched using the second patterned masking layer as a mask to form: an inductor trench exposing the planar copper interconnect bottom half of a stacked spiral inductor; a MIM capacitor trench exposing at least a portion of the metal top plate and at least a portion of the planar copper interconnect contact point of a MIN capacitor; and routing point trenches exposing the two exposed planar copper interconnect routing points of a precision resistor. The inductor trench, MIM capacitor trench and the routing point trenches are filled with planarized metal to complete formation of the following devices as selected: the spiral inductor within the spiral inductor area; the MIM capacitor within the MIM capacitor area; and the precision resistor within the precision resistor area.